The present application relates generally to the electrical, electronic and computer arts and, more particularly, to finned semiconductor structures employed in the fabrication of FinFET devices, vertical transistor devices, and other electronic devices.
Fin-type field-effect transistors (FinFETs) have three-dimensional, non-planar configurations including fin-like structures extending vertically above substrates. The substrates may include semiconductor on insulator (SOI) substrates or bulk semiconductor substrates. Silicon fins are formed in some FinFETs on substrates via known technology such as sidewall image transfer (SIT). FinFET structures including SOI substrates can be formed, in part, by selectively etching the crystalline silicon layers down to the oxide or other insulating layers thereof following photolithography. Active fin heights are set by SOI thickness when employing SOI substrates. In bulk FinFETs, active fin height is set by oxide thickness and etched fin height. Impurities can be introduced below the fins to provide a punch through stop (PTS). Punch through isolation of fins in bulk FinFET devices is provided to avoid leakage and is typically formed with the well implant. A relatively deep implant is required for relatively tall fins. The gates of FinFETs can be formed using a “gate-first” process wherein a gate stack and spacers are formed prior to selective epitaxial growth wherein source and drain regions are enlarged. A “gate-last” process may alternatively be employed wherein the source/drain regions are formed following fin patterning.
Nanosheet FETs have been under development for possible use in tight pitch applications such as 7 nm nodes and beyond. Such FETs include multiple channel layers, each channel layer being separated by a gate stack including a layer of electrically conductive gate material and a gate dielectric layer. The gate stacks wrap around all sides of the channel layers, thereby forming a gate-all-around (GAA) structure. Epitaxial regions on the ends of the nanosheet channel layers form source/drain regions of the nanosheet FETs. Spacers are employed for electrically isolating the gates from the source/drain regions of nanosheet transistors.
Vertical field-effect transistors (VFETs) are characterized by doped, possibly vertical channel regions, p-n junctions on one or more sides of the channels, and ohmic contacts forming the source and drain regions vertically rather than horizontally.
Both nFET and pFET devices are often formed on the same substrate. In CMOS integration, nFET and pFET devices have different immunities from short channel effects (SCEs) as well as different source/drain resistances due to different dopant diffusion rates under the same thermal conditions. For multi-gate devices such as FinFETs, electron-hole mobility cannot be optimized at a single cross-fin dimension (Dfin) due to the different scattering mechanisms.
FinFET, vertical transistors and nanosheet transistors can benefit by using different Dfin for pFET and nFET devices. Typically pFET devices should have smaller Dfin in view of relatively poor SCEs immunity. Hole mobility is less sensitive to Dfin thus smaller Dfin for PFET devices is desirable. Relatively thin fins could be obtained using an additional patterning and fin trimming process. However, the additional lithography required would increase cost and could introduce defects that might affect yield. The fin trimming process, if through oxidation/etching, could cause vertical non-uniformity problems.